Memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written or read in a higher current mode. A predetermined number of cells are located in a row between each of a plurality of upper and lower word lines and another predetermined number of cells are located in a column between a plurality of bit lines. In other words, each cell is uniquely coupled between a combination of word lines and bit lines.
A row of cells is selected when increased voltage is supplied to the upper word line. A particular cell in that row is read by a sense amplifier coupled to the bit lines. A first read current through one bit line flows directly to the sense amplifier. A second read current through the other bit line flows through one side of the memory cell to the upper word line. When a cell is written, the first read current is directed through the cell and the second read current is directed to the sense amplifier.
The sense amplifier typically comprises a pair of differentially connected transistors responsive to the voltage on the bit lines and having a current carrying electrode of each transistor coupled in some manner to an output. Conventional memory sense amplifiers were entirely bipolar or MOS (metal-oxide-semiconductor) circuits that provided the relative merits of each. Bipolar sense amplifiers provide fast gate speeds, narrow transition widths and reduced delay per unit load. CMOS sense amplifiers provide high noise immunity, high input impedance, low power requirements, but a wider transition width. However, a large CMOS structure is required when driving large capacitive loads and in most cases, several stages of scaled CMOS inverters are necessary in order to minimize the total delay. For BIMOS memories having a large number of devices, it is desirable that each MOS device be of small size. As the size of a MOS device is reduced, the transconductance of the device and consequently the ability to drive a heavy capacitive load is also reduced. Bipoler devices continue to be used for driving these capacitive loads due to their high current gain. In quiesent periods, the bipolar push-pull transistors do not dissipate power. During transient periods, the bipolar current gain allows faster charging and discharging of capactive loads. This results in a significant decrease in metal and fanout delays.
Attempts to combine bipolar and MOS technology to achieve all of these results have been numerous in recent years. Furthermore, smaller CMOS devices may be used in the BIMOS circuit than those required in an all-CMOS device circuit.
One previously known memory sense amplifier combining bipolar and MOS technologies was disclosed in "A High-Speed 64K CMOS RAM with Bipolar Sense Amplifiers", IEEE JOURNAL OR SOLID-STATE CIRCUITS, Vol. SC-19, No. 5, October 1984, page 559, FIG. 5(c). A first pair of differentially connected bipolar transistors have their bases coupled for receiving current from the bit lines of a memory circuit. The emitters of the first pair of differentially connected bipolar transistors have their emitters connected to the bases of a second pair of differentially connected bipolar transistors. The collectors of the second pair of differentially connected bipolar transistors are connected to the gates of a pair of differentially connected MOS transistors having current supplied thereto by a MOS current mirror. The drain of one of the differentially connected MOS transistors is connected to an output amplifier.
However, this circuit suffers from long delays and the need for two CMOS stages to obtain adequate output drive.
Thus, what is needed is a BIMOS memory sense amplifier having the low power dissipation and high noise immunity of CMOS devices while maintaining the high drive capability and switching speed associated with bipolar devices.